EEET2162 / 2035-Advance Digital Design1 Report – Engineering Assignment Help

Assignment Task


Laboratory Project

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(i) To design, simulate, implement and test a digital circuit using the Quartus Prime toolchain.
(ii) To demonstrate the workflow when using the Verilog HDL to construct a design for a physical Field Programmable Gate Array (FPGA) target.
(iii) To develop a hierarchical design where an emphasis is placed on the development of small sub-modules which can be replicated to form a complete system.
(iv) To develop a large-scale Verilog HDL project that will require numerous submodules that are required to work together to achieve a common complex task.

Students are expected to work in pairs and submit a combined report / Verilog project which will be assessed by the Course Coordinator. The projects will run for four weeks (Weeks 8, 9, 10, 11), however the submissions and demonstration will occur in Week 12. Students will need to strictly
select a project partner from the same laboratory session (whether online or face-to-face classes) and in the same course.
The aim of the projects is to allow groups (maximum of two) of students to build relatively complex designs in Verilog HDL that can be deployed on the DE-10 Nano Development Platform. All work must be original, and plagiarism will be taken very seriously. The projects are expected to require approximately 36 hours per student to be completed successfully.

The topics have also been devised to allow students with varying skill levels to select a project that is suitable for their knowledge. The entire assessment (report and demonstration) will be scaled according to the difficulty level. As the semester is not yet complete, not all relevant material has been presented, however all students should have enough knowledge to begin working on the actual topic as of week 8. More details will be presented during the remainder of the lecture series. The topics and outcomes presented in Section 3.0 are non-negotiable and students must select from the provided list unless a prior arrangement has been made with the Course Coordinator. Furthermore, students are required to inform their Laboratory Demonstrator as to which project they have selected.

a) HDMI processing and overlay (on-screen display) using the Cyclone V 

Difficulty Level: Distinction.

The DE-10 Nano Development Platform contains an Analog Devices ADV7513 HDMI Transmitter. This particular device is connected to the FPGA using a 24-bit wide bus as well as an array of control signals. The aim of this project is to use both the FPGA and the ADV7513 to produce an on-screen display.
As an example, an image can be loaded into the onboard RAM (FPGA or SoC DDR3 RAM) and then displayed over the HDMI interface. Once the image has been loaded an onscreen overlay should present some user-configurable text over the image. Whilst a static image is acceptable, higher marks will be awarded to students who can display a moving image loaded from one of the other interfaces available on the development platform.
The ADV7513 also contains a series of configuration registers which will need to be made accessible over an interface such as I2C.

b) Platform Designer implementation of an SPI communication interface

Difficulty Level: High Distinction.

One issue with the DE-10 Nano Development Platform is that it is quite difficult to interface with using standardised interfaces such as SPI or I2C. This is due to the fact that the FPGA needs to be configured with a block that contains the required functionality as the Hard Processor System (HPS) contains limited external interfaces. In this project, students will need to develop a configurable width (minimum 1-bit, maximum 32-bits) SPI interface that can be used to transmit data / receive data. A maximum serial clock (SCLK) of 25MHz is required.

It is suggested that the interface is modelled on a standard ARM processor such as the STM32F4. Note that IP Blocks (with the exception of a PLL) are not permitted in this project. The system is also required to interface with the HPS embedded in the Cyclone V. Additional material will be made available that discusses the software drivers required to communicate with an Avalon Memory Mapped Slave via Platform Designer.
At a minimum, the developed SPI peripheral should be able to have the clock phase and polarity configured, the number of bits transmitted / received configurable and have the ability to act as a master or slave device.

c) Audio signal capture and processing using the onboard ADC.

Difficulty Level: High Distinction.

As the need for real-time processing of multiple channels of audio data increases with more advanced musical instruments many manufacturers are beginning to use FPGAs to perform data processing. This is mainly due to the fact that FPGAs can have multiple parallel data paths that can process each signal independently. If signals need to be combined, then a final stage can be used to synchronise the audio sources as well as perform and further processing such as equalisation.

The aim of this project will to be capture four channels of audio data using the onboard LTC2308 produced by Analog Devices. A Fast Fourier Transform (using an IP Block) is to then be used on the incoming data and an audio level spectrum analyser developed. The audio signal FFT is to be displayed over the HDMI interface. Additional hardware will be required to interface the audio sources to the LTC header on the DE-10 Nano Development Platform. Please see the course coordinator for the additional resources if this project is selected.

d) ATmega32A Emulation.

Difficulty Level: High-Distinction.

This project requires students to develop a functionally equivalent micro-controller design that executes a reduced version of the instruction set of the ATmega32A. For the complete instruction set please see the Microchip website ( For simplicity, the design does not have to maintain the 4-state timing of the ATmega32A but the implementation must maintain its single level pipelining characteristic. Students will need
to investigate techniques to implement the program and data memories.

Omit the reset timer, power-on reset and watchdog circuits. A suggested partitioning is shown below:
Sub-task 1 = Memory and I/O section (includes program memory I-reg & RAM)
Sub-task 2 = All timing functions (includes Timer0 and watchdog – omit power-on reset)
Sub-task 3 = CPU functions.

e) Floating-point Unit Development

Difficulty Level: Credit.

In this project, students are required to develop a structural Floating-Point Unit (FPU) for use with a microprocessor. The processor needs to be capable of floating-point addition and multiplication. The numbers are to be encoded into IEEE 754 single precision 32-bit format. The FPU should also be able to detect and flag the ‘NaN’ cases. For the project demonstration, interface the FPU to the DE-10 RAM and perform the operation
(A* B) + C on 1000 data triplets (A, B, C). Transfer the results back to the RAM, then upload to the PC for display. Verify the results by comparing them with another method (e.g., C program, spreadsheet etc.). It is essential that an external interface is used to transfer the data back to a host PC.

4 Assessment Schedule
To assess the project both a combined final technical report and group presentation / demonstration are required. 

a) Project Technical Report Students are required to individually submit a final project technical report (maximum of twelve (15) pages in body of report) describing the work undertaken during the project. The report should be written in such a way that it can be read and understood by another Engineer with a background in FPGA design and development. Note that the same report is to be submitted by both group members. 

As a general guideline the project report should include, but not be limited to, the following sections:

  • Title page: include the project title, the date, student ID and name(s) and the revision number.
  • Acknowledgements: note (and references) any IP blocks or source code.
  • Executive summary: state the main achievements of the project. This is a summary of key findings, achievements, and measurements. It is not an introduction. The words limit is 150.
  • Table of contents: section titles and page numbers for your report.
  • Introduction: provide an overview and define the scope of the project.
  • Literature search: a brief indication of what references and external information were sought and used. The literature review should be limited to technical information that is relevant to explain the concepts and problems addressed in the project.
  • Technical work and Results (Students may choose own section titles here): this part may contain a description of the process used to develop the deliverables and a complete description of what has been created. Students can elaborate on their contribution to the project and compare obtained results with those in literature or other known solutions. A clear delineation should exist between existing techniques and solutions and student work. A comparison should be undertaken against the original deliverables of the project and what has been delivered. If discrepancies exist then the reasons should be elaborated (even incorrect or unexpected results and still worth discussing). This section should form the bulk of the report. Technical content may include state diagrams, relevant truth-tables and block diagrams explaining the HDL used in realising the solution. A discussion should be held on the HDL modules developed and their interconnections. Simulation results can also be included in the report to explain / demonstrate project outcomes.
  • Discussion and Conclusion: Students should provide a discussion of the (simulation) results, clearly stating their achievements, lessons learnt and possible future works.
  • References: All references quoted in the report (where relevant) should be listed down in the manner and style indicated below and numbered sequentially in the order as they appear in the main text. However, the list should not contain any entry that has not been quoted anywhere in the report. The IEEE reference format is to be used.
  • Appendices: These must also be properly titled and should contain details which are of secondary importance in understanding the report. Examples include program listings, schematics and detailed specifications of important components. Note that the full HDL solution does not need to appear in the appendices as it is to be submitted electronically.

b) Project Technical Demonstration
Students will be required to demonstrate their complete project to the Course Coordinator in Week 12 at their scheduled time. Each student group will have approximately seven (7) minutes to describe and demonstrate their technical achievements. A further three (3) minutes will be made available for questions. Additional material, such as diagrams and images can be used to support the discussion. The demonstration component accounts for 15% of the overall subject grade and will be individually graded. Note that the demonstration is informal and will generally involve viewing the project outcomes around one of the laboratory computers. Students are requested to ensure that their project is functional prior to the assessment time. No time compensation will be given if the project is not ready to view at the schedule time.

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